Conversation

Notices

1. Nate Cull (natecull@mastodon.social)'s status on Friday, 08-Apr-2022 01:39:44 UTC Nate Cull

   This is interesting: CHERI (Capability Hardware Enhanced RISC Instructuctions)

   A CPU architecture which does capabilities down at the memory-address level, like they should have been done decades ago.

   https://www.cl.cam.ac.uk/research/security/ctsrd/cheri/

   • Santa Claes 🇸🇪🇭🇰🎅 likes this.
   • theruran 🌐🏴 (theruran@hackers.town)'s status on Friday, 08-Apr-2022 01:39:52 UTC theruran 🌐🏴

     in reply to

     @natecull there's a RISC-V version in the works too

     Santa Claes 🇸🇪🇭🇰🎅 likes this.