Qualcomm, NXP, etc #riscv joint venture? Interesting.
Notices tagged with riscv
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Santa Claes 🇸🇪🇭🇰🎅 (clacke@libranet.de)'s status on Friday, 11-Aug-2023 03:40:13 UTC Santa Claes 🇸🇪🇭🇰🎅 -
LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Tuesday, 16-May-2023 07:17:40 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} https://www.theregister.com/2022/08/31/arm_sues_qualcomm/ [www theregister com]
https://www.cnbc.com/2022/09/01/why-arms-lawsuit-against-qualcomm-is-a-big-deal.html [www cnbc com]
#ARM sued #Qualcomm last Summer over differing interpretations of licenses. The case may speed up moves to build upon #RISC-V instead of ARM. -
LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Saturday, 31-Dec-2022 02:12:04 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} #Risc-V based #Lichee-Pi 4A claims competitive performance with !RasPi 4B https://www.cnx-software.com/2022/12/27/lichee-pi-4a-risc-v-sbc-raspberry-pi-4-th1520-processor/ [www cnx-software com] In conversation from nu.federati.net permalink Attachments
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LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Friday, 11-Feb-2022 01:37:16 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} I did recently look at #RISC-V SBCs, but they were all fairly expensive crowdsource projects and none of them seemed even comparable to a #Raspberry_Pi.
I saw one board that is supposed to be on a similar level to an #Arduino Duo ... but they didn't say whether it could be programmed with the same Arduino software.
If I can get compute board and not just a microcontroller, I'd like to try to learn some more about programming in a RISC-V environment.In conversation from nu.federati.net permalink -
LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Monday, 24-Jan-2022 23:43:07 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} https://www.digikey.gr/en/blog/a-novel-twist-maxim-integrated-removes-risk-of-risc-v [www digikey gr]
#Microcontroller combines #ARM and #RISC-V coresIn conversation from nu.federati.net permalink Attachments
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LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Sunday, 06-Dec-2020 00:16:20 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} @geniusmusing You probably found this during your search, but if not: https://riscv.org/blog/2020/11/picorio-the-raspberry-pi-like-small-board-computer-for-risc-v/
#risc-v #sbc #open_source_hardware !raspiIn conversation from nu.federati.net permalink Attachments
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LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} (lnxw48a1@nu.federati.net)'s status on Saturday, 05-Dec-2020 14:54:56 UTC LinuxWalt (@lnxw48a1) {3EB165E0-5BB1-45D2-9E7D-93B31821F864} #RISC-V CPU claims record-breaking performance per Watt; beats #ARM, #X86. https://arstechnica.com/gadgets/2020/12/new-risc-v-cpu-claims-recordbreaking-performance-per-watt/ [arstechnica com] In conversation from nu.federati.net permalink Attachments
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jjg (jjg@social.coop)'s status on Thursday, 27-Sep-2018 00:06:54 UTC jjg I got into #riscv when I found out that #ARM wasn’t as open as I thought it was.
Now that I’m learning more about it I’m finding out that RISC-V is awesome in so many ways in addition to being an open design.
I’m getting really excited about finding ways to work it into my designs...
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h@social.coop's status on Saturday, 05-May-2018 05:29:47 UTC h Microsemi announced a “HiFive Unleashed Expansion Board” built on its PolarFire FPGA that adds PCIe and USB expansion for the RISC-V-based, Linux driven HiFive Unleashed SBC.
http://linuxgizmos.com/fpga-based-add-on-board-brings-pcie-to-the-first-linux-based-risc-v-sbc/
cc: @vertigo @jjg @LinuxSocist
#microsemi #pcie #fpga #hifive #riscv #sbc #linuxIn conversation from social.coop permalink -
Hallå Kitteh (clacke@social.heldscal.la)'s status on Sunday, 15-Apr-2018 06:05:30 UTC Hallå Kitteh > The good news is that there is an anonymous sponsor willing to help cut through this. The anonymous sponsor has - believe it or not - paid for an SDCard Association membership so that, under NDA, a contractor can be paid to implement a BSD-licensed SD/MMC and eMMC hard macro! Various other plans are underway, I can’t say more at the moment.
> If there are any people who have experience with MyHDL, Verilog, Bluespec (BSV), cocotb, FPGA prototyping, processor architecture and design, please do get in touch: there’s a budget available for the right people willing to release or work on BSD-licensed RTL, to help get a truly libre-licensed RISC-V Soc with 3D graphics and video decode capability into production.
https://www.crowdsupply.com/eoma68/micro-desktop/updates/ddr3-ram-and-a-libre-risc-v-soc
@vertigo maybe this is interesting to you?
#riscvIn conversation from social.heldscal.la permalink -
Hallå Kitteh (clacke@social.heldscal.la)'s status on Friday, 23-Feb-2018 03:20:26 UTC Hallå Kitteh There are people out there who want to work on porting #racket and/or #chez to #riscv. Awesome to hear.
https://www.mail-archive.com/racket-users@googlegroups.com/msg37339.htmlIn conversation from social.heldscal.la permalink -
h@social.coop's status on Sunday, 18-Feb-2018 19:53:13 UTC h RISC-V Go Port
Home of the RISC-V port of the Go programming language
https://github.com/riscv/riscv-go
I don't know what's the maturity, coverage, or completeness of this project, but it's already great news that it exists at all.
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Hallå Kitteh (clacke@social.heldscal.la)'s status on Thursday, 04-Jan-2018 03:21:43 UTC Hallå Kitteh @vertigo I guess #riscv, being RISC, doesn't have much of a pipeline and probably didnt have to do this kind of optimization.
Lets just drop legacy and all move over to the future.In conversation from social.heldscal.la permalink -
Hallå Kitteh (clacke@social.heldscal.la)'s status on Tuesday, 02-Jan-2018 16:40:43 UTC Hallå Kitteh @ralph @xj9 Sure is. @vertigo here is working on some really cool stuff, and has a web page with all the right heartwarming buzzwords.
#kestrel #riscv
https://kestrelcomputer.github.io/kestrelIn conversation from social.heldscal.la permalink -
Hallå Kitteh (clacke@social.heldscal.la)'s status on Monday, 01-Jan-2018 08:08:45 UTC Hallå Kitteh @vertigo Are you awake? Would you be interested to come on #hprny Mumble (see https://social.heldscal.la/notice/5472625 ) and talk about your #riscv stuff? In conversation from social.heldscal.la permalink Attachments
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Hallå Kitteh (clacke@social.heldscal.la)'s status on Wednesday, 27-Dec-2017 06:13:41 UTC Hallå Kitteh For new readers: #kestrel in this context means https://kestrelcomputer.github.io/kestrel , #riscv and fully-free-hardware goodness!
@vertigo A demo scene for fully free hardware would be awesome.In conversation from social.heldscal.la permalink Attachments
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Hallå Kitteh (clacke@social.heldscal.la)'s status on Tuesday, 12-Dec-2017 02:18:21 UTC Hallå Kitteh @schestowitz Wow, that is amazing.
Watching the talk now: https://www.youtube.com/watch?v=ATZls4lbwmM
#riscv
/cc @grainloom @satchmoz @vertigo @koodaIn conversation from social.heldscal.la permalink Attachments
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Linux (linux@linuxrocks.online)'s status on Sunday, 10-Dec-2017 14:20:19 UTC Linux SiFive are on a path towards making libre RiscV CPUs.
RISC-V is an open, free ISA enabling a new era of processor innovation through OPEN standard collaboration.
Naturally then, these are coming with libre firmware. Rumor has it they'll be available late 2018. These should be both more libre than libreboot devices (since the hardware is o/s as well) and faster (64-bit, multicore).
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In conversation from linuxrocks.online permalink Attachments
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Dr. Roy Schestowitz (罗伊) (schestowitz@gnusocial.de)'s status on Thursday, 07-Dec-2017 01:53:08 UTC Dr. Roy Schestowitz (罗伊) #WesternDigital Gives A Billion Unit Boost To Open Source #RISCV CPU https://gnusocial.de/url/4621902 In conversation from gnusocial.de permalink Attachments
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heise online (inoffiziell) (heiseonline@squeet.me)'s status on Friday, 01-Dec-2017 19:05:29 UTC heise online (inoffiziell) Künftige Controller für Speichersysteme von WD setzen auf Künstliche Intelligenz und die offene Architektur RISC-V, um höhere Leistung und neue Funktionen zu realisieren. https://www.heise.de/newsticker/meldung/Western-Digital-entwickelt-RISC-V-Controller-fuer-Festplatten-mit-Transmeta-Gruender-3906996.html #Controller #EmbeddedSystems #Prozessoren #RISC-V #Transmeta #WD #WesternDigital In conversation from squeet.me permalink Attachments